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| A License Plate Recognition (LPR) smart camera application example is provided to let you start with FoRTReSS methodology on a realistic example. Detailed application description is available in [1]. | A License Plate Recognition (LPR) smart camera application example is provided to let you start with FoRTReSS methodology on a realistic example. Detailed application description is available in [1]. | ||
| + | License Plate Recognition overview (Thales Research & Technology) | ||
| {{:plate_detection_overview.jpg?nolink&600|}} | {{:plate_detection_overview.jpg?nolink&600|}} | ||
| - | License Plate Recognition overview - | ||
| - | Thales Research & Technology | ||
| Download and extract the following archive: | Download and extract the following archive: | ||
| - | [[http://fortress-toolbox.unice.fr/Apps.tar.gz|DOWNLOAD LINK]] | + | [[http://five-sigma.com/tmp/standalone_versions/Apps.tar.gz|DOWNLOAD LINK]] |
| - | Open FoRTReSS. In the main menu, select File -> Open -> Project, browse for example to ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/'' and select ''fortress.prj''. Everything is already set up to process a working simulation. However you can explore different parameters from Menu FoRTReSS -> Preferences such as: | + | Open FoRTReSS. In the main menu, select File -> Open -> Project, browse for example to ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/'' and select ''fortress.prj''. Everything is already set up to process a working simulation. However you can explore different parameters from menu FoRTReSS -> Preferences such as: |
| * FPGA target device (FoRTReSS parameters / selected device). Valid FPGA devices are currently ''xc6vlx240t'', ''xc7z020'' and ''xc7z045''. | * FPGA target device (FoRTReSS parameters / selected device). Valid FPGA devices are currently ''xc6vlx240t'', ''xc7z020'' and ''xc7z045''. | ||
| * Scheduling algorithm (FoRTReSS Parameters / Scheduler Strategy): ''EA3c'' is the default heterogeneous Hw / Sw scheduler detailed in [1]. You may also use AMAP_EDF, which is a standard EDF scheduler, for comparison. | * Scheduling algorithm (FoRTReSS Parameters / Scheduler Strategy): ''EA3c'' is the default heterogeneous Hw / Sw scheduler detailed in [1]. You may also use AMAP_EDF, which is a standard EDF scheduler, for comparison. | ||
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| * Number of cores (Processor Parameters) | * Number of cores (Processor Parameters) | ||
| * Number of instanciated applications (Application Parameters) | * Number of instanciated applications (Application Parameters) | ||
| - | * Hardware task implementations (Task Report/Netlist) | + | * Hardware task implementations (Task Report / Netlist) |
| To run simulation: | To run simulation: | ||
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| Simulation takes about half an hour. You can ignore the error code at the end of simulation. | Simulation takes about half an hour. You can ignore the error code at the end of simulation. | ||
| - | To check the results: | + | To analyze the results: |
| * Open GTKWave (''sudo apt-get install gtkwave'') | * Open GTKWave (''sudo apt-get install gtkwave'') | ||
| * In the main menu select File -> Open New Tab and select ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/Config Seq/Solutions/solution_1_RZ_2.vcd''. This solution is based on 2 MicroBlaze cores and 1 Reconfigurable Region. | * In the main menu select File -> Open New Tab and select ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/Config Seq/Solutions/solution_1_RZ_2.vcd''. This solution is based on 2 MicroBlaze cores and 1 Reconfigurable Region. | ||
| * Then go to File -> Read Save File -> ''TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/Config Seq/gtk-trace.gtkw''. This configuration file is predefined to display a selection of meaningful signals. | * Then go to File -> Read Save File -> ''TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB/Config Seq/gtk-trace.gtkw''. This configuration file is predefined to display a selection of meaningful signals. | ||
| - | * You can then use GTKWave tools to locate the end of function ''IMG_write'' in the second hyperperiod denoting the termination of the last function in the application hyperperiod (then simulation waits for the activation of the next hyperperiod). The corresponding absolute time should indicate ''44,713s''. Execution time is therefore ''10,713s'' (''44,713s - 34s'') after removing the ''34s'' duration of the first hyperperiod, and the corresponding Hyper Instant Energy is ''12,307J''. | + | * You can then use GTKWave features to locate the end of function ''IMG_write'' in the second hyperperiod denoting the termination of the last function in the second hyperperiod (then the system is idle until the activation of the next hyperperiod). The corresponding absolute time should indicate ''44,713s''. Execution time is therefore ''10,713s'' (''44,713s - 34s'') after removing the ''34s'' duration of the first hyperperiod, and the corresponding Hyper Instant Energy is ''12,307J''. |
| - | Previous exploration outputs various other DPR accelerated solutions for 2 MicroBlaze cores and a number of Reconfigurable Regions increasing from 1 to 11. Then you may want to compare with a full software solution based only on 4 MicroBlaze cores: | + | Previous exploration outputs various other DPR accelerated solutions for 2 MicroBlaze cores and a number of Reconfigurable Regions increasing from 1 to 11. |
| + | |||
| + | You may want to compare with a full software solution (based on 4 MicroBlaze cores): | ||
| * Open and simulate project ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_SW/'' | * Open and simulate project ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_SW/'' | ||
| - | * In the main menu select File -> Open New Tab and select ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_SW/Config Seq/Solutions/solution_0_RZ_2.vcd''. The corresponding execution time should be ''48,008s'' and instant energy ''52,219J''. The corresponding improvement factor in terms of energy delay product is 19: ''(52,219*48,008)/(12,307*10,713)''. | + | * In the main menu select File -> Open New Tab and select ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_SW/Config Seq/Solutions/solution_0_RZ_2.vcd''. The corresponding execution time should be ''48,008s'' and instant energy ''52,219J''. The corresponding improvement factor in terms of energy delay product is ''(52,219*48,008)/(12,307*10,713) = 19''. |
| You can also compare against static hardware solutions (i.e. 2 cores + reconfigurable accelerators without DPR) with project ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_STATIC/'' | You can also compare against static hardware solutions (i.e. 2 cores + reconfigurable accelerators without DPR) with project ''Apps/TRT_XC6VLX240T_MB/1-LANE_LPR/TRT_XC6VLX240T_MB_STATIC/'' | ||
| - | Each time you want to run another simulation with a given FoRTReS project, first go to FoRTReSS -> Preferences -> Clean All Generated Files -> Current config to erase previous simulation files (simulations can generate several giga bytes of simulation data). | + | Each time you want to run another simulation with a given FoRTReSS project, first go to FoRTReSS -> Preferences -> Clean All Generated Files -> Current config to erase previous simulation files (simulations can generate several giga bytes of result data). |
| - | Details underlying the methodology can be found in the [[Publications]] section, in particular the License Plate Recognition (LPR) application example and corresponding analysis of results are described in [1]. | + | Details underlying the methodology can be found in the [[Publications]] section, in particular the License Plate Recognition (LPR) application example and corresponding analysis of results are discussed in [1]. |
