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| * Power profiles and energy estimation based on practical CPU, FPGA and DPR models | * Power profiles and energy estimation based on practical CPU, FPGA and DPR models | ||
| * Detailed energy efficiency and mapping / scheduling analysis of Hw / Sw tasks | * Detailed energy efficiency and mapping / scheduling analysis of Hw / Sw tasks | ||
| - | * Methodology outline presented at | + | * Underlying methodology presentation at {{ :fetch2020.pdf |}} |
